The present invention generally relates to complimentary metal-oxide semiconductors (CMOS) and metal-oxide-semiconductor field-effect transistors (MOSFET), and more specifically, to gate stack fabrication.
The MOSFET is a transistor used for switching electronic signals. The MOSFET has a source, a drain, and gate electrode. The gate is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material, for example, silicon dioxide or high dielectric constant (high-k) dielectrics, which makes the input resistance of the MOSFET relatively high. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”).
N-type field effect transistors (nFET) and p-type field effect transistors (pFET) are two types of complementary MOSFETs. The nFET uses electrons as the current carriers and includes n-doped source and drain junctions. The pFET uses holes as the current carriers and includes p-doped source and drain junctions.
The FinFET is a type of MOSFET. The FinFET is a multiple-gate MOSFET device that mitigates the effects of short channels and reduces drain-induced barrier lowering. The “fin” refers to a semiconductor material patterned on a substrate that often has three exposed surfaces that form the narrow channel between source and drain regions. A thin dielectric layer arranged over the fin separates the fin channel from the gate. Because the fin provides a three dimensional surface for the channel region, a larger channel length can be achieved in a given region of the substrate as opposed to a planar FET device.
As CMOS scales to smaller dimensions, nanowire devices provide advantages. A nanowire is often suspended above the substrate by source/drain regions or the gate stack. Because the nanowire is suspended, the channel region of a nanowire device has 360 degrees of exposed area. The gate stack can be formed around the channel region of the nanowire to form a gate-all-around-device. The nanowire can provide even more surface area and greater channel length than a finFET device or planar FET device in a given region of a substrate. Nanowire FETs can be formed from stacked nanowires providing even greater layout density. Stacked nanowires provide, for example, increased drive current within a given layout area.
With the transistors scaling, the threshold voltage for different devices via the channel doping becomes more and more difficult for finFET devices, nanosheet devices and nanowire devices due to complex device structure as well as due to the maximum available Vt tuned by channel doping. Therefore, threshold voltage tuned by pure work function is needed to offer the different Vt type devices. In addition, due to the impurity scattering in the channel because of the need to have the channel doping to change the threshold voltage, the mobility of the transistors will be degraded and thus the performance will be impacted by channel doping to change the Vts. However, threshold voltage tuned by work function has no such issue because no channel doping is needed. And thus, threshold voltage tune by work function metal in the gate can offer different Vts but without performance degradation. Therefore, threshold voltage tune by work function metal in the gate become quite critical to have high performance chip.
Gate spacers form an insulating film along gate sidewalls. Gate spacers can also initially be formed along sacrificial gate sidewalls in replacement gate technology. The gate spacers are used to define source/drain regions in active areas of a semiconductor substrate located adjacent to the gate.
Device scaling in the semiconductor industry reduces costs, decreases power consumption, and provides faster devices with increased functions per unit area. Improvements in optical lithography have played a major role in device scaling. However, optical lithography has limitations for minimum dimensions and pitch, which are determined by the wavelength of the irradiation.